Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
299
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.3
Device 0 Function 0 Region DMIRCBAR
DMI Root Complex Registers Block (RCRB). This block is mapped into memory space, 
using register DMIRCBAR [Device 0:Function 0, offset 0x50].
14.3.1
DMIVC0RCAP
DMI VC0 Resource Capability 
Register name
Offset
Size
DMIVC0RCAP
0x10
32
DMIVC0RCTL
0x14
32
DMIVC0RSTS
0x1a
16
DMIVC1RCAP
0x1c
32
DMIVC1RCTL
0x20
32
DMIVC1RSTS
0x26
16
DMIVCPRCAP
0x28
32
DMIVCPRCTL
0x2c
32
DMIVCPRSTS
0x32
16
DMIVCMRCAP
0x34
32
DMIVCMRCTL
0x38
32
DMIVCMRSTS
0x3e
16
DMIVC1CDTTHROTTLE
0x60
32
DMIVCPCDTTHROTTLE
0x64
32
DMIVCMCDTTHROTTLE
0x68
32
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
0Function:0
Offset:
0x10
Bit
Attr
Default
Description
31:16
RO
0x0
maxtimeslots:
Max Time Slots  
15:15
RO
0x0
rejsnpt:
Reject Snoop Transactions  
0: Transactions with or without the No Snoop bit set within the TLP header 
are allowed on this VC.
1: Any transaction without the No Snoop bit set within the TLP header will be 
rejected as an Unsupported Request. 
14:0
RV
-
Reserved  
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