Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Cbo Functional Description
30
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
3.2
Source Address Decoder 
Within the Cbo, requests go through the Source Address Decoder (SAD) at the same 
time that they are allocating into the TOR and are sent to the LLC. Non-LLC message 
class types go through the SAD when they are allocating into the TOR as well.
The SAD receives the address, the address space, opcode, and a few other transaction 
details. It outputs the type of the target of the transaction (DRAM, MMIO, IO, LT, CFG) 
with proper NodeID or whether it should be serviced in the Local Crab (Ubox).
The SAD contains rules for the address decoding. Some of these rules are hardwired, 
and can be used before the SAD is initialized. Some rules must be enabled before they 
can be used. Some rules have parts that may be configured. 
3.2.1
System Address Spaces
The Intel Xeon processor E7 v2 product family cores and the IIO issue transactions to 
the memory address space, the I/O address space, and configuration address space.
Intel QPI virtual channels target the following address spaces:
• Hardware cache coherent address space, HOM
• Non-coherent (NC) address space, NCS/NCB
• I/O address space, IO
• PCI Express configuration address space, CFG
• LT special cycle address space, LT
HOM is used if the address is to be snooped. NC is used by the local or remote IIO if the 
address is not to be snooped. NC contains memory mapped I/O (MMIO) and various 
configuration register regions.
The processor always accesses system DRAM using the HOM channel, even if the 
memory type from the core is UC or WC. This allows the IA-32 preservation of memory 
type aliasing. 
The processor can access MMIO with memory type UC (Un-Cached), WP (Write 
Protected), WT (Write Through), or WC (Write Combining) using the NC channel. The 
processor can also access MMIO with WB (Write Back) however the core/software must 
be in place such that dirty data is never evicted to the Uncore for this range. The 
system does not implement hardware cache coherence in WP, WT, or WC, WB memory 
types; it is up to the programmer to maintain any needed cache coherence or memory 
ordering concerns with these memory types.
3.2.2
Uncore SAD Relationship to Other Address Decoders
3.2.2.1
Core Address Decoders
Addresses come from executing instructions and are translated by the segmentation 
and paging logic of the IA-32 core. The Cbo and the rest of Uncore always see host 
physical addresses.
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