Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
31
Datasheet Volume Two: Functional Description, February 2014
Cbo Functional Description
3.2.2.2
IIO Address Decoders
Although many of the address ranges for the IIO address decoders are now integrated 
into Cbo system address decoder, there are still significant portions of IIO address 
decoding logic that reside inside IIO. IIO Address decoders will provide protection, 
address translation and proper sub decoding to support IO related transactions. 
3.2.3
SAD Address Spaces
The memory address space primarily contains cache coherent DRAM. The DRAM 
decoder defines the location of the cache coherent DRAM segments of the system 
address map. It also contains MMIO, and many legacy address ranges. Legacy address 
ranges are decoded by the legacy address decoder and are described later. 
shows the system address map as seen by the SAD. 
Figure 3-1. SAD Address Map
No_ Early_ Go
Configuration
DRAM_ HI
TOHM
BOHM = 4 G
0
VGA hole
PAM hole
65536G
MMIOH
16 M
1 M
PCI Express
configuration
CSR_ PCIE
DRAM_ LO
FE 00_ 0000
1 _ 0000_ 0000
000 C _ 0000
000 A _ 0000
0010_ 0000
00 F 0 _ 0000
0100_ 0000
NO_
EARLY_ GO
DRAM
LEGACY
MMIO
TSeg Stolen Memory
FEC0_ 0000
CRAB
_ ABORT
Reserved
FEB8 _ 0000
FEB0_ 0000
IOAPIC
ICH
FLASH
FED0_ 0000
FF00_ 0000
MMIOL
LT
PCI Express Additional 
Segments
TSeg
Tseg
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