Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
310
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.4.1
VID
14.4.2
DID
14.4.3
PCICMD
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x0
Bit
Attr
Default
Description
15:0
RO
0x8086
vendor_identification_number:
The value is assigned by PCI-SIG to Intel.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x2
Bit
Attr
Default
Description
15:0
RO
0xe20 (Function 0)
0xe21 (Function 1)
0xe22 (Function 2)
0xe23 (Function 3)
0xe24 (Function 4)
0xe25 (Function 5)
0xe26 (Function 6)
0xe27 (Function 7)
RAID on Load:
0xe2e (Function 0)
0xe2f (Function 1)
device_identification_number:
Device ID values vary from function to function. Bits 
15:8 are equal to 0x0E.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x4
Bit
Attr
Default
Description
15:11
RV
-
Reserved. 
10:10
RW
0x0
intx_interrupt_disable:
Controls the ability of Intel® Quick Data DMA to generate legacy INTx 
interrupt (when legacy INTx mode is enabled).
1: Legacy Interrupt message generation is disabled
0: Legacy Interrupt message generation is enabled
If this bit transitions from 1->0 when a previous Assert_INTx message was 
sent but no corresponding Deassert_INTx message sent yet, a 
Deassert_INTx message is sent on this bit transition
9:9
RO
0x0
fast_back_to_back_enable:
Not applicable to PCI Express and is hardwired to 0
8:8
RO
0x0
serre:
This bit has no impact on error reporting from Intel® Quick Data DMA.
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