Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
311
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
7:7
RO
0x0
idsel_stepping_wait_cycle_control:
N/A
6:6
RO
0x0
perre:
This bit has no impact on error reporting from Intel® Quick Data DMA.
5:5
RO
0x0
vga_palette_snoop_enable:
Not applicable to internal IIO devices. Hardwired to 0.
4:4
RO
0x0
mwie:
Not applicable to internal IIO devices. Hardwired to 0.
3:3
RO
0x0
sce:
Not applicable to PCI Express. Hardwired to 0.
2:2
RW
0x0
bme:
This bit enables Intel® Quick Data DMA to generate memory write/MSI and 
memory read transactions.
1: Enables Intel® Quick Data DMA to generate memory read/write requests.
0: Intel® Quick Data DMA cannot generate new memory read/write 
requests. Those that are pending to be issued on the internal datapath on 
completion of an outstanding RFO, can be completed even if this bit is 0.
1:1
RW
0x0
mse:
1: Enables Intel® Quick Data DMA device’s memory BAR to be decoded as 
valid target address for accesses from OS/BIOS.
0: Disables Intel® Quick Data DMA device’s memory BAR to be decoded as 
valid target address for accesses from OS/BIOS.
Notes:
Any accesses via message channel or JTAG mini port to registers pointed to 
by the Intel® Quick Data DMA BAR address, are not gated by this bit being 
set that is, even if this bit is a 0, message channel/JTAG accesses to the 
registers pointed to by Intel® Quick Data DMA BAR address are 
allowed/completed normally. These accesses are accesses from internal 
microcode/PCU microcode and JTAG and they are allowed to access the 
registers normally even if this bit is clear.
0:0
RO
0x0
iose:
N/A
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x4
Bit
Attr
Default
Description
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