Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
318
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.4.16 MSIXCAPID
MSI-X Capability ID.
14.4.17 MSIXNXTPTR
MSI-X Next Pointer.
9:9
RWS
0x0
enable_no_snoop:
This bit is akin to the NoSnoop enable bit in the PCI Express capability 
register, only that this bit is controlled by bios rather than OS. When set, the 
no snoop optimization is enabled (provided the equivalent bit in the 
PCIExpress DEVCON register is set) on behalf of Intel® Quick Data DMA 
otherwise it is not.
Notes:
Due to severe performance degradation, it is not recommended that this bit 
be set except in debug mode.
8:8
RV
-
Reserved1:
Reserved.
7:4
RWS
0x0
numrd:
This register controls how many CL-size memory read requests that the DMA 
engine can have outstanding to main memory. Setting this field to 0h will 
allow maximum number of reads to be outstanding. Setting this to a value 
other than 0h (max 15 or Fh) will allow only that many memory reads to be 
outstanding.
3:0
RWS
0xf
numrfo:
This register controls how many RFOs the DMA engine can have outstanding 
to main memory. Setting this field to 0h will allow maximum number of RFOs 
to be outstanding. Setting this to a value other than 0h (max 15 or Fh) will 
allow only that many RFOs to be
outstanding.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0
Offset:
0x60
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x80
Bit
Attr
Default
Description
7:0
RO
0x11
cb_msixcapid:
Assigned by PCI-SIG for MSI-X (Intel® Quick Data DMA)
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x81
Bit
Attr
Default
Description
7:0
RO
0x90
cb_msixnxtptr:
This field is set to 90h for the next capability list (PCI Express capability 
structure) in the chain.
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