Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
321
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.4.24 DEVCAP
The PCI Express Device Capabilities register identifies device specific information for 
the device.
7:4
RO
0x9
device_port_type:
This field identifies the type of device. It is set to for the DMA to indicate root 
complex integrated endpoint device.
3:0
RO
0x2
capability_version:
This field identifies the version of the PCI Express capability structure. Set to 
2h for PCI Express and DMA devices for compliance with the extended base 
registers.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x92
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x94
Bit
Attr
Default
Description
31:29
RV
-
Reserved:
28:28
RWS_O
0x0
flr_supported:
27:26
RO
0x0
captured_slot_power_limit_scale:
Does not apply to Intel® Quick Data DMA
25:18
RO
0x0
captured_slot_power_limit_value:
Does not apply to Intel® Quick Data DMA
17:16
RV
-
Reserved. 
15:15
RO
0x1
role_based_error_reporting:
IIO is 1.1 compliant and so supports this feature
14:14
RO
0x0
power_indicator_present_on_device:
Does not apply to Intel® Quick Data DMA
13:13
RO
0x0
attention_indicator_present:
Does not apply to Intel® Quick Data DMA
12:12
RO
0x0
attention_button_present:
Does not apply to Intel® Quick Data DMA
11:9
RO
0x0
endpoint_l1_acceptable_latency:
N/A
8:6
RO
0x0
endpoint_l0s_acceptable_latency:
N/A
5:5
RO
0x0
extended_tag_field_supported:
downloadlike
ArtboardArtboardArtboard
Report Bug