Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
322
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.4.25 DEVCON
The PCI Express Device Control register controls PCI Express specific capabilities 
parameters associated with the device.
4:3
RO
0x0
phantom_functions_supported:
Intel® Quick Data DMA does not support phantom functions.
2:0
RO
0x0
max_payload_size:
Intel® Quick Data DMA supports max 128B on writes to PCIExpress
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x94
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x98
Bit
Attr
Default
Description
15:15
RW
0x0
initiate_flr:
Intel® Quick Data DMA does a reset of that function only per the FLR ECN. 
This bit always returns 0 when read and a write of 0 has no impact
14:12
RO
0x0
max_read_request_size:
N/A to Intel® Quick Data DMA since it does not issue tx on PCIE
11:11
RW
0x1
enable_no_snoop:
For Intel® Quick Data DMA, when this bit is clear, all DMA transactions must 
be snooped. When set, DMA transactions to main memory can utilize No 
Snoop optimization under the guidance of the device driver.
10:10
RO
0x0
auxiliary_power_management_enable:
Not applicable to Intel® Quick Data DMA
9:9
RO
0x0
phantom_functions_enable:
Not applicable to Intel® Quick Data DMA since it never uses phantom 
functions as a requester.
8:8
RO
0x0
extended_tag_field_enable:
7:5
RO
0x0
max_payload_size:
N/A for Intel® Quick Data DMA
4:4
RW
0x0
enable_relaxed_ordering:
For most parts, writes from Intel® Quick Data DMA are relaxed ordered, 
except for DMA completion writes. But the fact that Intel® Quick Data DMA 
writes are relaxed ordered is not very useful except when the writes are also 
non-snooped. If the writes are snooped, relaxed ordering does not provide 
any particular advantage based on IIO uArch. But when writes are non-
snooped, relaxed ordering is required to get good BW and this bit is expected 
to be set. If this bit is clear, NS writes will get terrible performance.
3:3
RO
0x0
unsupported_request_reporting_enable:
N/A for Intel® Quick Data DMA
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