Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
328
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
This register controls severity of uncorrectable DMA unit errors between fatal and non-
fatal.
14.4.34 DMAUNCERRPTR
DMA Cluster Uncorrectable Error Pointer.
14.4.35 DMAGLBERRPTR
DMA Cluster Global Error Pointer.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0
Offset:
0x150
Bit
Attr
Default
Description
31:13
RV
-
Reserved. 
12:12
RWS
0x0
syndrome:
Multiple errors
11:11
RV
-
Reserved. 
10:10
RWS
0x0
read_address_decode_error_severity:
9:8
RV
-
Reserved. 
7:7
RWS
0x1
rd_cmpl_header_error_severity:
6:4
RV
0x1
Reserved:
3:3
RWS
0x1
dma_internal_hw_parity_error_severity:
2:2
RWS
0x0
received_poisoned_data_from_dp_severity:
1:0
RV
-
Reserved. 
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0
Offset:
0x154
Bit
Attr
Default
Description
7:5
RV
-
Reserved. 
4:0
ROS_V
0x0
uncerrptr:
Points to the first unmasked uncorrectable error logged in the 
DMAUNCERRSTS register. This field is only valid when the corresponding 
error is unmasked and the status bit is set and this register is rearmed to 
load again once the error pointed by this field in the uncorrectable error 
status register is cleared.Value of 0x0 corresponds to bit 0 in 
DMAUNCERRSTS register, value of 0x1 corresponds to bit 1 and so forth.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0
Offset:
0x160
Bit
Attr
Default
Description
7:4
RV
-
Reserved. 
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