Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
344
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.5.17 CHANSTS_1
Channel Status 1 Register.
The Channel Status Register records the address of the last descriptor completed by 
the DMA channel. Refer to Intel® Quick Data Architecture Specification for special 
hardware requirements when software reads this register.
14.5.18 CHAINADDR_0
Descriptor Chain Address 0 Register.
This register is written by the processor to specify the first descriptor to be fetched by 
the DMA channel.
14.5.19 CHAINADDR_1
Descriptor Chain Address 1 Register.
This register is written by the processor to specify the first descriptor to be fetched by 
the DMA channel.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x8c
Bit
Attr
Default
Description
31:0
RO
0x0
cmpdscaddr:
This register stores the upper address bits (64B aligned) of the last descriptor 
processed. The DMA channel automatically updates this register when an 
error or successful completion occurs. For each completion, the DMA channel 
over-writes the previous value regardless of whether that value has been 
read.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x90
Bit
Attr
Default
Description
31:0
RW_L
0x0
dscaddrlo:
This 64 bit field marks the address of the first descriptor to be fetched by the 
DMA channel. The least significant 6 bits must be zero for the address to be 
valid.
This register is RW if CHANCNT register is 1 otherwise this register is RO.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x94
Bit
Attr
Default
Description
31:0
RW_L
0x0
dscaddrhi:
This 64 bit field marks the address of the first descriptor to be fetched by the 
DMA channel. The least significant 6 bits must be zero for the address to be 
valid.
This register is RW if CHANCNT register is 1 otherwise this register is RO.
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