Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
347
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
6:6
RW1CS
0x0
cdata_parerr:
Chipset Data Parity Error. The DMA channel sets this bit 
indicating that the current transfer has encountered a parity 
error reported by the chipset. When this bit has been set, the 
address of the failed descriptor is in the Channel Status 
register.
5:5
RW1CS
0x0
chancmd_err:
CHANCMD Error. The DMA channel sets this bit indicating that 
a write to the CHANCMD register contained an invalid value 
(e.g. more than one command bit set).
4:4
RW1CS
0x0
chn_addr_valerr:
Chain Address Value Error. The DMA channel sets this bit 
indicating that the CHAINADDR register has an illegal address 
including an alignment error (not on a 64-byte boundary).
3:3
RW1CS
0x0
descriptor_error:
The DMA channel sets this bit indicating that the current 
transfer has encountered an error (not otherwise covered 
under other error bits) when reading or executing a DMA 
descriptor. When this bit has been set and the channel returns 
to the Halted state, the address of the failed descriptor is in 
the Channel Status register.
2:2
RW1CS
0x0
nxt_desc_addr_err:
Next Descriptor Address Error. The DMA channel sets this bit 
indicating that the current descriptor has an illegal next 
descriptor address including an alignment error (not on a 64-
byte boundary). When this bit has been set and the channel 
returns to the Halted state, the address of the failed 
descriptor is in the Channel Status register.
1:1
RW1CS
0x0
dma_xfrer_daddr_err:
DMA Transfer Destination Address Error. The DMA channel 
sets this bit indicating that the current descriptor has an 
illegal destination address. When this bit has been set, the 
address of the failure descriptor has been stored in the 
Channel Status register.
0:0
RW1CS
0x0
dma_trans_saddr_err:
DMA Transfer Source Address Error. The DMA channel sets this 
bit indicating that the current descriptor has an illegal source 
address. When this bit has been set, the address of the failure 
descriptor has been stored in the Channel Status register.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0xa8
Bit
Attr
Default
Description
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