Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
353
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.5.34 MSGUPADDR
MSI-X Upper Address Registers.
14.5.35 MSGDATA
MSI-X Data Registers.
14.5.36 VECCTRL
MSI-X Vector Control Registers.
14.5.37 PENDINGBITS
MSI-X Interrupt Pending Bits Registers.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x2004
Bit
Attr
Default
Description
31:0
RW_V
0x0
chmsgupaddr_const:
Reserved to 0 because does not apply to IA. This field is RW for compatibility 
reason only.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x2008
Bit
Attr
Default
Description
31:0
RW_V
0x0
chmsgdata:
Specifies the vector that needs to be used for interrupts from the DMA 
engine. IIO uses the lower 16 bits of this field to form the data portion of the 
interrupt on the coherent interface. The upper 16 bits are not used by IIO 
and left as RW only for compatibility reasons.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x200c
Bit
Attr
Default
Description
31:1
RO
0x0
chvecctrlcnst:
1
0:0
RW_V
0x1
chmask:
When a bit is set, the channel is prohibited from sending a message, even if 
all other internal conditions for interrupt generation are valid.
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