Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
362
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.6.18 MMCFG_BASE
MMCFG Address Base
14.6.19 MMCFG_LIMIT
MMCFG Address Limit.
2:0
RW
0x0
clr_hdrmfd:
When set, function#0 with in the indicated device shows a value of 0 for bit 7 
of the HDR register, indicating a single function device. BIOS sets this bit, 
when only function#0 is visible within the device, either because SKU reasons 
or BIOS has hidden all functions but function#0 within the device via the 
DEVHIDE register.
Bit 0 is for Device#1
Bit 1 is for Device#2
Bit 2 is for Device#3
Currently this is defined only for devices 1, 2 and 3 because in other devices 
it is expected that at least 2 functions are visible to OS or the entire device is 
hidden.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x80
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x84
Bit
Attr
Default
Description
31:26
RW_LB
0x3f
mmcfg_base_addr:
Indicates the base address which is aligned to a 64 MB boundary. 
25:0
RV
-
Reserved. 
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x88
Bit
Attr
Default
Description
31:26
RW_LB
0x0
mmcfg_limit_addr:
Indicates the limit address which is aligned to a 64MB boundary. Any access 
that decodes to be between MMCFG.BASE<= Addr <= MMCFG.LIMIT 
targets the MMCFG region and is aborted by IIO. 
Address bits[25:0] are ignored and may be any value.
Address bits[63:32] must be 0.
Setting the MMCFG.BASE greater than MMCFG.LIMIT, disables this region. 
25:0
RV
-
Reserved. 
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