Intel E7-8891 v2 CM8063601377422 User Manual

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

363

Datasheet Volume Two: Functional Description, February 2014

Generic Protected Memory Range X Base Address. (X = 1, 0)

63:52

RW_LB

0x0

limit:

Indicates the limit address which is aligned to a 1MB boundary.
Any access to falls within TSEG.BASE[31:20] <= Addr[31:20] <= 

TSEG.LIMIT[31:20] is considered to target the Tseg region and IIO aborts 

it.

Note that address bits 19:0 are ignored and not compared. The result is 

that BASE[19:0] is effectively 00000h and LIMIT is effectively FFFFFh.

Setting the TSEG.BASE greater than the limit, disable this region.

51:32

RV

-

Reserved. 

31:20

RW_LB

0xfe0

base:

Indicates the base address which is aligned to a 1MB boundary. Bits [31:20] 

corresponds to A[31:20] address bits.

19:0

RV

-

Reserved. 

63:51

RV

-

Reserved.

50:16

RW_LB

0x7ffffffff

base_address:

[50:16] of generic memory address range that needs to be protected from 

inbound dma accesses. The protected memory range can be anywhere in 

the memory space addressable by the processor. Addresses that fall in this 

range that is, GenProtRange.Base[63:16] <= Address [63:16] <= 

GenProtRange.Limit [63:16], are completer aborted by IIO.
Setting the Protected range base address greater than the limit address 

disables the protected memory region. Note that this range is orthogonal to 

Intel

®

VT-d spec defined protected address range.

Since this register provides for a generic range, it can be used to protect 

any
system dram region or MMIO region from DMA accesses. But the expected 

usage for this range is to abort all PCIe* accesses to the PCI-Segments 

region.

15:0

RV

-

Reserved.