Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
366
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.6.27 NCMEM_BASE
Noncoherent Memory Base Address.
14.6.28 NCMEM_LIMIT
Noncoherent Memory Limit.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0xe0
Bit
Attr
Default
Description
63:26
RW_LB
0x3ffffffff
addr:
Noncoherent memory base address. Describes the base address of a 64MB 
aligned dram memory region on Intel
®
QPI that is not coherent. Address 
bits [63:26] of an inbound address if it satisfies ’NcMem.Base[63:26] <= 
A[63:26] <= NcMem.Limit[63:26]’ is considered to be towards the 
noncoherent Intel
®
QPI memory region. This means that IIO cannot ever 
use ’allocating’ write commands for accesses to this region, over IDI. This, 
in effect, means that DCA/TH writes cannot ever target this address region. 
The range indicated by the noncoherent memory base and limit registers 
does not necessarily fall within the low dram or high dram memory regions 
as described via the corresponding base and limit registers. 
Usage Model for this range is ROL. Accesses to this range default to NSWr 
and NSRd accesses on Intel
®
QPI. But accesses to this range will use non-
allocating reads and writes, when enabled. 
This register is programmed once at boot time and does not change after 
that, including any quiesce flows 
25:0
RV
-
Reserved.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0xe8
Bit
Attr
Default
Description
63:26
RW_LB
0x0
addr:
Noncoherent memory limit address. Describes the limit address of a 64 MB 
aligned dram memory region on Intel
®
QPI that is noncoherent. Address 
bits [63:26] of an inbound address if it satisfies ’NcMem.Base[63:26] <= 
A[63:26] <= NcMem.Limit[63:26]’ is considered to be towards the 
noncoherent Intel
®
QPI memory region. This means that IIO cannot ever 
use ’allocating’ write commands for accesses to this region, over IDI. This in 
effect means that DCA/TH writes cannot ever target this address region. 
The range indicated by the noncoherent memory base and limit registers 
does not necessarily fall within the low dram or high dram memory regions 
as described via the corresponding base and limit registers. 
This register is programmed once at boot time and does not change after 
that, including any quiesce flows. 
25:0
RV
-
Reserved.
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