Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
368
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.6.32 LMMIOL_BASE
Local MMIO Low Base.
14.6.33 LMMIOL_LIMIT
Local MMIO Low Limit.
15:8
RW_LB
0x0
bus1:
Is the internal bus# of rest of uncore. All devices are claimed by UBOX on 
behalf of this component. Devices that do not exist within this component 
on this bus number are master aborted by the UBOX.
7:0
RW_LB
0x0
bus0:
Is the internal bus# of IIO and also PCH. Configuration requests that target 
Devices 16-31 on this bus number must be forwarded to the PCH by the 
IIO. Devices 0-15 on this bus number are claimed by the UBOX to send to 
IIO internal registers. UBOX master aborts devices 8-15 automatically, 
since these devices do not exist.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x108
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x10c
Bit
Attr
Default
Description
15:8
RW_LB
0x0
base:
Corresponds to A[31:24] of MMIOL base address. An inbound memory 
address that satisfies ‘local MMIOL base[15:8] <= A[31:24] <= local MMIOL 
limit[15:8]’ is treated as a local peer-to-peer transaction that do not cross 
coherent interface.
Note:
Setting LMMIOL.BASE greater than LMMIOL.LIMIT disables local MMIOL 
peer-to-peer.
This register is programmed once at boot time and does not change after 
that, including any quiesce flows. 
7:0
RV
-
Reserved.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x10e
Bit
Attr
Default
Description
15:8
RW_LB
0x0
limit:
Corresponds to A[31:24] of MMIOL limit. An inbound memory address that 
satisfies ‘local MMIOL base[15:8] <= A[31:24] <= local MMIOL limit[15:8]’ 
is treated as a local peer-to-peer transaction that does not cross the 
coherent interface.
Note:
Setting LMMIOL.BASE greater than LMMIOL.LIMIT disables local MMIOL 
peer-to-peer.
This register is programmed once at boot time and does not change after 
that, including any quiesce flows.
7:0
RV
-
Reserved.
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