Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
369
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.6.34 LMMIOH_BASE
Local MMIO High Base.
14.6.35 LMMIOH_LIMIT
Local MMIO High Limit.
14.6.36 CIPCTRL
Coherent Interface Protocol Control.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x110
Bit
Attr
Default
Description
63:51
RV
-
Reserved.
50:26
RW_LB
0x0
base:
Corresponds to A[50:26] of MMIOH base. An inbound memory address that 
satisfies local MMIOH base [50:26] <= A[63:26] <= local MMIOH limit 
[50:26] is treated as a local peer-to-peer transaction that does not cross 
the coherent interface.
Notes:
Setting LMMIOH.BASE greater than LMMIOH.LIMIT disables local MMIOH 
peer-to-peer.
This register is programmed once at boot time and does not change after 
that, including any quiesce flows.
25:0
RV
-
Reserved.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x118
Bit
Attr
Default
Description
63:51
RV
-
Reserved.
50:26
RW_LB
0x0
limit:
Corresponds to A[50:26] of MMIOH limit. An inbound memory address that 
satisfies local MMIOH base [50:26] <= A[63:26] <= local MMIOH limit 
[50:26] is treated as local a peer-to-peer transactions that does not cross 
the coherent interface.
Notes:
Setting LMMIOH.BASE greater than LMMIOH.LIMIT disables local MMIOH 
peer-to-peer.
This register is programmed once at boot time and does not change after 
that, including any quiesce flows.
25:0
RV
-
Reserved.
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