Intel E7-8891 v2 CM8063601377422 User Manual

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Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
Home Agent Functional Description
iMC Interface
The HA operates at the same frequency as Cbo in the uncore clock domain, whereas 
the iMC is operated at the fixed DRAM clock domain, called Dclock domain. 
The HA sends the DRAM reads, writes, and other commands to the MC interface. It 
receives the return data, completion, error signals, and other request and 
acknowledgements from the MC. 
HA to MC Interface
The HA can send a request to MC when the request acquired its MC credit and the BGF 
allows to store the requester on its available HA to MC control BGF input buffer. The 
control interface is a shared by all memory channels between the HA and MC. The 
control interface BGF is a non-backpressure BGF. The HA writes to control BGF when 
the BGF input buffer is valid and the HA has a write credit. It assumes the MC receives 
the command after given clock cycles.
Each memory channel has its own data interface individually. Each memory channel 
interface consists of an individual data BGF. T The MC write credit can only be credited 
back to the credit pool after the HA received the ack back from the MC. The channel is 
decoded based on rules programmed in the Target Address Decoder (TAD). 
Target Address Decode (TAD)
The target address decoder is responsible for resolving the channel interleave based on 
the system address decoding results. The target address decode assumptions and 
mechanism are consistent with the system address decode (SAD) at Cbo and the 
memory address decode (MAD) at MC.
The system address decoder (SAD) is responsible for mapping the address to the Home 
Agent. It occurs before the request is sent to the Home Agent. The target address 
decode (TAD) is responsible for the logical channel address mapping and interleaving at 
Home Agent. The target address decoder is located at the Home Agent. The memory 
address decode at MC will map the channel address to meet DRAM requirements.
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