Intel E7-8891 v2 CM8063601377422 User Manual
Integrated I/O (IIO) Configuration Registers
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
Whenever this bit is written to 1 (regardless what the current value of this bit
is), IRP block first clears bit 0 in CIPSTS register and takes a snapshot of the
currently pending write transactions to dram in Write Cache, wait for them to
complete fully (that is, deallocate the corresponding Write Cache/RRB entry)
and then set bit 0 in CIPSTS register.
Whenever this bit is written to 1, this implies wr$ snapshot request was due
to ADR. This is a status indication and does not cause the snapshot to occur.
When set, PCIWriteUpdate command is never issued on IDI and the writes
that triggered this flow would be treated as “normal” writes and the rules
corresponding to the “normal writes” apply.
This is the MSB bit for the rrbsize. The lower 3-bits of the rrbsize reside in
This is the BIOS programmed field that indicates the “SocketID” of this
particular socket. “SocketID” is the unique value that each socket in the
system gets for DCA/DIO target determination. Normally this value is the
same as the APICID[7:5] of the cores in the socket, but it can be other
values as well, if system topology were to not allow that straight mapping.
IIO uses strapped NodeID to compare against the target NodeID determined
by using the target SocketID value as a lookup into the CIPDCASAD register.
If there is a match, then a PCIDCAHint is not sent (since the data is already
located in the same LLC).
This register is not used for this comparison. It is not used by hardware at