Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
372
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.6.37 CIPSTS
Coherent Interface Protocol Status.
14.6.38 CIPDCASAD
Coherent Interface Protocol DCA Source Address Decode.
0:0
RW
0x0
pcirdcurr_drduc_sel:
On Inbound Coherent Reads selection of RdCur or DRd is done based on this 
configuration bit.
0: PCIRdCurrent
1: DRd.UC
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x140
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x144
Bit
Attr
Default
Description
31:3
RV
-
Reserved.
2:2
RO_V
0x1
rrb_non_phold_arb_empty:
This indicates that there are no pending requests in the RRB with the 
exception of ProcLock / Unlock messages to the lock arbiter.0 - Pending RRB 
requests
1 - RRB Empty except for any pending Proclock / Unlock
This is a live bit and hence can toggle clock by clock. This is provided mostly 
as a debug visibility feature.
1:1
RO_V
0x1
rrb_empty:
This indicates that there are no pending requests in the RRB.0 - Pending RRB 
requests
1 - RRB Empty
This is a live bit and hence can toggle clock by clock. This is provided mostly 
as a debug visibility feature.
0:0
RO_V
0x0
flush_pending_writes:
This bit gets cleared whenever bit 31 in CPICTRL is written to 1 by software 
and gets set by h/w when the pending writes in the Write Cache (at the time 
bit 31 in CIPCTRL is written to 1 by software) complete that is, the Write 
Cache/RRB entry is deallocated for all those writes.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x148
Bit
Attr
Default
Description
31:29
RW
0x0
dcalt7:
For a TPH/DCA request, specifies the target NodeID[2:0] when the inverted 
Tag[2:0] is 7
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