Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
376
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.6.43 VTGENCTRL2
Intel
®
VT-d General Control 2.
14:8
RV
-
Reserved.
7:4
RW_LB
0xa
hpa_limit:
Represents the host processor addressing limit
0000: 2^36 (that is, bits 35:0)
0001: 2^37 (that is, bits 36:0)
...
1010: 2^46 (that is, bits 45:0)
When Intel
®
VT-d translation is enabled on a Intel
®
VT-d engine, all host 
addresses (during page walks) that go beyond the limit specified in this 
register will be aborted by IIO. Note that pass-through and “translated” ATS 
accesses carry the host-address directly in the access and are subject to 
this check as well.
3:0
RW_LB
0x8
gpa_limit:
Represents the guest virtual addressing limit for the nonisochronous 
Intel
®
VT-d engine.
0000: 2^40 (that is, bits 39:0)
0001: 2^41 (that is, bits 40:0)
..
0111: 2^47
1000: 2^48
Others: Reserved
When Intel
®
VT-d translation is enabled, all incoming guest addresses from 
PCI Express, associated with the nonisochronous Intel
®
VT-d engine, that 
go beyond the limit specified in this register will be aborted by IIO and a UR 
response returned. This register is not used when translation is not enabled. 
Note that “translated” and “pass-through” addresses are in the “host-
addressing” domain and NOT “guest-addressing” domain and hence 
GPA_LIMIT checking on those accesses are bypassed and instead 
HPA_LIMIT checking applies.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x184
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x18c
Bit
Attr
Default
Description
31:19
RV
-
Reserved:
18:12
RW_LB
0x0
tlb_free_entry_limit:
Retry prefetch request when number of entries available for allocation in the 
IOTLB is less than the programmed value.
11:11
RW_LB
0x0
lructrl:
Controls what increments the LRU counter that is used to degrade the LRU 
bits in the IOTLB, L1/L2, and L3 caches.
0: Count Cycles (same as TB)
1: Count Requests
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