Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
385
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
24:24
RW
0x0
disable_all_allocating_flows:
When this bit is set, IIO will no more issue any new inbound IDI command 
that can allocate into LLC. Instead, all the writes will use one of the non-
allocating commands - PCIWiL/PCIWiLF/PCINSWr/PCINSWrF. Software 
should set this bit only when no requests are being actively issued on IDI. 
So either a lock/quiesce flow should be employed before this bit is 
set/cleared or it should be set up before DMA is enabled in system.
23:23
RV
-
Reserved.
22:22
RW
0x0
disable_ro_on_writes_from_cb_dma:
21:21
RV
-
Reserved.
20:20
RW
0x0
switch_arbitration_weight_for_CB_DMA:
Switch Arbitration Weight for Intel® Quick Data DMA.
When set, Intel® Quick Data DMA arbitration weight is treated equivalent 
to a x16 PCIe* port. When clear, it is equivalent to a x8 PCIe* port. 
Note: It is recommended that this bit never be set.
19:19
RW
0x0
rvgaen:
Remote VGA Enable. Enables VGA accesses to be sent to remote node.
If set, accesses to the VGA region (A_0000 to B_FFFF) will be forwarded to 
the CBo where it will determine the node ID where the VGA region resides. 
It will then be forwarded to the given remote node.
If clear, then VGA accesses will be forwarded to the local PCIe* port that 
has its VGAEN set. If none have their VGAEN set, then the request will be 
forwarded to the local DMI port, if operating in DMI mode. If it is not 
operating in DMI mode, then the request will be aborted.
18:18
RW
0x1
disable_inbound_ro_for_vc0:
When enabled this mode will treat all inbound write traffic as RO = 0 for 
VC0. This affects all PCI Express ports,the DMI port, and internal Intel® 
Quick DataDMA engine.
0 - Ordering of inbound transactions is based on RO bit for VC0
1 - RO bit is treated as '0' for all inbound VC0 traffic
Note that this pretty much impacts only the NS write traffic because for 
snooped traffic RO bit is ignored by h/w. When this bit is set, the NS write if 
enabled BW is going to be generally bad.
Note that this bit does not impact VC1 and VCm writes
17:16
RW
0x1
dmi_vc1_write_ordering:
Mode is used to control VC1 write traffic from DMI (Intel
®
VT).
00: Reserved
01: Serialize writes on CSI issuing one at a time
10: Pipeline writes on CSI except for writes with Tag value of 0x21 which 
are issued only after prior writes have all completed and reached global 
observability
11: Pipeline writes on CSI based on RO bit, that is, if RO = 1, pipeline a 
write on Intel
®
QPI without waiting for prior write to have reached global 
observability. If RO=0, then it needs to wait till prior writes have all reached 
global observability.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x1c0
Bit
Attr
Default
Description
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