Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
39
Datasheet Volume Two: Functional Description, February 2014
iMC Functional Description
5
iMC Functional Description
5.1
Overview
The Intel Xeon processor E7 v2 product family implements two internal memory 
controllers (iMC). Each memory controller supports two Intel SMI 2 interfaces and two 
Intel C102/C104 Scalable Memory Buffer expansion per iMC. Intel C102/C104 Scalable 
Memory Buffer provides support for two DDR3 buses. Intel SMI 2 is the technology 
used covering communication across the iMC and Intel C102/C104 Scalable Memory 
Buffer silicon.
The memory controller can be configured to operate in one of two modes:
• Independent mode: The performance mode. Each DDR3 channel is addressed 
individually via burst lengths of 8 bytes. The Intel SMI channel will operate at twice 
the DDR3 data rates.
• Lockstep mode: The high RAS mode supporting DDDC with x4 DRAMs. The 
memory controller handles all cache lines across two DDR3 channels behind one 
Intel C102/C104 Scalable Memory Buffer. The Intel SMI 2 channel operates at the 
DDR3 transfer rate.
The processor iMC will interface with the rest of the uncore via the Home Agent (HA), 
each socket will have two iMC’s instantiated per processor die, each with its own HA.
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