Intel E7-8891 v2 CM8063601377422 User Manual

396

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

5:3

RW_L

0x6

cbo_ndr_cdt_threshold:

2:0

RW_L

0x4

qpi_ndr_cdt_threshold:

These are the total credits allocated for NDR packets.

NDR to Intel

®

QPI requests

If more than one credit is used, a credit from the vc0_rd_cdt_threshold pool 

will be used.
A credit from this pool will be used.

The first credit out of this pool is not shared with vc0_rd_cdt_threshold, but 

all additional credits are shared from that pool.

31:31

RW_L

0x0

dbg_entry_num_sel_bit6:

Notes:
Locked by DBGBUSLCK

30:29

RW_L

0x0

disable_wr_merge_flush_hang_fix:

Performance optimization to induce a flush when a write merged entry has P 

F allocated to a different entry. Normally aging timer rollover would have to 

trigger the flush. This change will accelerate the flush in lieu of aging timer 

rollover. Should only be used when write combining is enabled. This is only 

for IRP0.

“00”: Disable performance optimization
“11”: Enable performance optimization
Locked by DBGBUSLCK