Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
398
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.6.60 IRP_MISC_DFX3
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x854
Bit
Attr
Default
Description
31:31
RW_L
0x0
dbg_entry_num_sel_bit6:
Notes:
Locked by DBGBUSLCK
30:29
RW_L
0x0
disable_wr_merge_flush_hang_fix:
Performance optimization to induce a flush when a write merged entry has P 
F allocated to a different entry. Normally aging timer rollover would have to 
trigger the flush. This change will accelerate the flush in lieu of aging timer 
rollover. Should only be used when write combining is enabled. This is only 
for IRP1.
"00": Disable performance optimization
"11": Enable performance optimization
Locked by DBGBUSLCK
28:16
RW_L
0x1fff
ctagentry_avail_mask:
This feature will mask out write cache entries in strides of 8. Each bit maps 
to the
relevant write cache entries noted below:
bit0: write cache entries 7 down to 0 Note: This bit should always be set to 
'1'
bit1: write cache entries 15 down to 8
bit2: write cache entries 23 down to 16
bit3: write cache entries 31 down to 24
bit4: write cache entries 39 down to 32
bit5: write cache entries 47 down to 40
bit6: write cache entries 55 down to 48
bit7: write cache entries 63 down to 56
bit8: write cache entries 71 down to 64
bit9: write cache entries 79 down to 72
bit10: write cache entries 87 down to 80
bit11: write cache entries 95 down to 88
bit12: write cache entries 103 down to 96
where a bit is defined as:
'0': Mask out write cache entries
'1': Don’t mask out write cache entries
This mode should not be used in conjunction with rrbsize mode in CIPCTRL.
15:15
RW_L
0x0
bogus_wr_for_second_p_pf_after_wrpull:
Sup re ss bogus write-back if second P PF for write mergeable case comes in 
after WritePull for first P PF.
14:14
RV
-
Reserved:
13:13
RW_L
0x0
drop_ncs_with_error:
Drop outbound NCS messages that have errors in formatting. Do not forward 
to Switch. This is consistent with Intel Xeon processor E7-2800/4800/8800 
v2 product family Product Family behavior.
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