Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
iMC Functional Description
40
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
The iMC logic runs at the DDR CLK frequency to match the DDR bandwidth. 
The HA runs at Uncore CLK frequency like the rest of the uncore. 
5.2
Operation
5.2.1
Overview
The iMC unit contains four controllers. Up to four channels can be operated 
independently or DDR Channels behind Intel C102/C104 Scalable Memory Buffer can 
be paired for lockstep operation. The DRAM controllers share a common address 
decode and DMA engines for RAS features.
Configuration registers may be per channel or common. Each DRAM controller has a 
scheduler, write and read data paths, ECC logic and auxiliary structures.
Figure 5-1. Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family Memory 
Interface
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