Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
409
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.7.8
VTD[0:1]_FLTSTS
Intel
®
VT-d Fault Status.
15:0
RW
0x0
domain_id:
Indicates the id of the domain whose context-entries needs to be selectively 
invalidated. S/W needs to program this for both domain and device selective 
invalidates. The processor ignores bits 15:8 since it supports only a 8 bit 
Domain ID. 
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:0
Offset:
0x28
, 0x1028
Bit
Attr
Default
Description
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:0
Offset:
0x34
, 0x1034
Bit
Attr
Default
Description
31:16
RV
-
Reserved.
15:8
ROS_V
0x0
fault_record_index:
This field is valid only when the Primary Fault Pending field is set. This field 
indicates the index (from base) of the fault recording register to which the 
first pending fault was recorded when the Primary Fault pending field was set 
by hardware.
7:7
RV
-
Reserved.
6:6
RW1CS
0x0
invalidation_timeout_error:
Hardware detected a Device-IOTLB invalidation completion timeout. At this 
time, a fault event may be generated based on the programming of the Fault 
Event Control register.
5:5
RW1CS
0x0
invalidation_completion_error:
Hardware received an unexpected or invalid Device-IOTLB invalidation 
completion. At this time, a fault event is generated based on the 
programming of the Fault Event Control register. 
4:4
RW1CS
0x0
invalidation_queue_error:
Hardware detected an error associated with the invalidation queue. For 
example, hardware detected an erroneous or unsupported Invalidation 
Descriptor in the Invalidation Queue. At this time, a fault event is generated 
based on the programming of the Fault Event Control register.
3:2
RV
-
Reserved.
1:1
ROS_V
0x0
primary_fault_pending:
This field indicates if there are one or more pending faults logged in the fault 
recording registers. Hardware computes this field as the logical OR of Fault 
(F) fields across all the fault recording registers of this DMA-remap hardware 
unit.0: No pending faults in any of the fault recording registers
1: One or more fault recording registers has pending faults. The fault 
recording index field is updated by hardware whenever this field is set by 
hardware. Also, depending on the programming of fault event control 
register, a fault event is generated when hardware sets this field.
0:0
RW1CS
0x0
primary_fault_overflow:
Hardware sets this bit to indicate overflow of fault recording registers
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