Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
413
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.7.17 VTD[0:1]_PROT_HIGH_MEM_LIMIT
Intel
®
VT-d Protected Memory High Limit.
14.7.18 VTD[0:1]_INV_QUEUE_HEAD
Intel
®
VT-d Invalidation Queue Header Pointer.
14.7.19 VTD[0:1]_INV_QUEUE_TAIL
Intel
®
VT-d Invalidation Queue Tail Pointer.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:0
Offset:
0x78
, 0x1078
Bit
Attr
Default
Description
63:21
RW
0x0
addr:
16 MB aligned limit address of the high protected DRAM region
Note that Intel
®
VT-d engine generated reads/writes (page walk, interrupt 
queue, invalidation queue read, invalidation status) themselves are allowed 
toward this region, but no DMA accesses (non-translated DMA or ATS 
translated DMA or pass through DMA, that is, no DMA access of any kind) 
from any device is allowed toward this region (regardless of whether TE is 0 
or 1), when enabled.
20:0
RV
-
Reserved.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:0
Offset:
0x80
, 0x1080
Bit
Attr
Default
Description
63:19
RV
-
Reserved.
18:4
RO_V
0x0
queue_head:
Specifies the offset (128-bit aligned) to the invalidation queue for the 
command that will be fetched next by hardware. This field is incremented 
after the command has been fetched successfully and has been verified to be 
a valid/supported command.
3:0
RV
-
Reserved.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:0
Offset:
0x88, 0x1088
Bit
Attr
Default
Description
63:19
RV
-
Reserved.
18:4
RW
0x0
queue_tail:
Specifies the offset (128-bit aligned) to the invalidation queue for the 
command that will be written next by software. 
3:0
RV
-
Reserved.
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