Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
414
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.7.20 VTD[0:1]_INV_QUEUE_ADD
Intel
®
VT-d Invalidation Queue Address.
14.7.21 VTD[0:1]_INV_COMP_STATUS
Intel
®
VT-d Invalidation Completion Status.
14.7.22 NONISOCH_INV_CMP_EVTCTRL
Invalidation Completion Event Control.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:0
Offset:
0x90
, 0x1090
Bit
Attr
Default
Description
63:12
RW
0x0
invreq_queue_base_address:
This field points to the base of size-aligned invalidation request queue.
11:3
RV
-
Reserved.
2:0
RW
0x0
queue_size:
This field specifies the length of the invalidation request queue. The number 
of entries in the invalidation queue is defined as 2^(X + 8), where X is the 
value programmed in this field. 
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:0
Offset:
0x9c
, 0x109c
Bit
Attr
Default
Description
31:1
RV
-
Reserved.
0:0
RW1CS
0x0
invalidation_wait_descriptor_complete:
Indicates completion of Invalidation Wait Descriptor with Interrupt Flag (IF) 
field set. Hardware clears this field whenever it is executing a wait descriptor 
with IF field set and sets this bit when the descriptor is complete. 
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:0
Offset:
0xa0
Bit
Attr
Default
Description
31:31
RW
0x1
inval_nonisoch_msgmsk:
0: No masking of interrupt. When a invalidation event condition is detected, 
hardware issues an interrupt message (using the Invalidation Event Data & 
Invalidation Event Address register values).
1: This is the value on reset. Software may mask interrupt message 
generation by setting this field. Hardware is prohibited from sending the 
interrupt message when this field is set.
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