Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
434
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.8.25 ERRPINDAT
This register provides the data value when the error pin is configured as a general 
purpose output. 
0:0
RW1CS
0x0
pin0:
This bit is set upon the transition of deassertion to assertion of the Error pin. 
Software write 1 to clear the status. Hardware will only set this bit when the 
corresponding ERRPINCTL field is set to 10b.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5
Function:
2
Offset:
0xa8
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5
Function:
2
Offset:
0xac
Bit
Attr
Default
Description
31:3
RV
-
Reserved.
2:2
RW_LB
0x0
pin2:
This bit acts as the general purpose output for the Error[2] pin. Software 
sets/clears this bit to assert/deassert Error[2] pin. This bit applies only when 
ERRPINCTL[5:4] = 01; otherwise it is reserved.
0: Assert ERR#[2] pin (drive low)
1: Deassert ERR#[2] pin (float high)
Notes:
This pin is open drain and must be pulled high by external resistor when 
deasserted.
BIOS needs to write 1 to this bit for security reasons if this register is not 
used.
1:1
RW_LB
0x0
pin1:
This bit acts as the general purpose output for the Error[1] pin. Software 
sets/clears this bit to assert/deassert Error[1] pin. This bit applies only when 
ERRPINCTL[3:2] = 01; otherwise it is reserved.
0: Assert ERR#[1] pin (drive low)
1: Deassert ERR#[1] pin (float high)
Notes:
This pin is open drain and must be pulled high by external resistor when 
deasserted.
BIOS needs to write 1 to this bit for security reasons if this register is not 
used.
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