Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
437
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.8.29 VPPMEM
11:0
RWS
0x9c4
vpp_tsu_thd:
Represents the high time and low time of the SCL pin. It should be set to 
5uS for a 100 kHz SCL clock 5uS high time and 5uS low time. The default 
value represents 5 uS with an internal clock of 500 MHz.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:2
Offset:
0xc0
Bit
Attr
Default
Description
63:40
RV
-
Reserved:
39:32
RWS
0x0
vpp_en:
When set, the VPP function for the corresponding root port is enabled. 
Enable Root 
Port
[39]
reserved.
[38]
reserved.
[37]
reserved.
[36]
reserved.
[35]
Memory Channel 3
[34]
Memory Channel 2
[33]
Memory Channel 1
[32]
Memory Channel 0
31:0
RWS
0x0
vpp_enaddr:
Assigns the VPP address of the device on the VPP interface and assigns the 
port address for the ports within the VPP device. There are for memory 
channel hot-plug.
Port  Addr  
Root Port
[31]  [30:28]
 Reserved
[27]  [27:24]
 Reserved
[23]  [22:20]
 Reserved
[19]  [18:16]
 Reserved
[15]  [14:12]
 Memory Channel 3
[11]  [10:8]
 Memory Channel 2
[7]    [6:4]
 Memory Channel 1
[3]    [2:0]
 Memory Channel 0
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5
Function:
2
Offset:
0xbc
Bit
Attr
Default
Description
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