Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
439
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.8.31 GFERRMASK
Global Fatal Error Mask.
This register masks the reporting of fatal errors detected by the IIO local interfaces. An 
individual error control bit that is set masks error signaling of the particular local 
interface; software may set or clear the mask bit.
Note that bit fields in this register can become reserved depending on the port 
configuration. For example, if the PCIe* port is configured as 2X8 ports, then only the 
corresponding PCIe* X8 bit fields are valid.
1:1
RW1CS
0x0
irp1_err_msk:
IRP1 Coherent Interface Error Mask
0:0
RW1CS
0x0
irp0_err_msk:
IRP0 Coherent Interface Error Mask
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:2
Offset:
0x19c
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:2
Offset:
0x1a0
Bit
Attr
Default
Description
31:26
RV
-
Reserved4:
Reserved.
25:25
RW1CS
0x0
vtd_err_msk:
Intel® VT-d Error Mask
24:24
RW1CS
0x0
mi_err_msk:
Miscellaneous Error Mask
23:23
RW1CS
0x0
iio_err_msk:
IIO Core Error Mask
22:21
RV
-
Reserved3:
Reserved
20:20
RW1CS
0x0
dmi_err_msk:
DMI Error Mask
19:16
RV
-
Reserved2:
Reserved
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