Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
440
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.8.32 GCERRMASK
Global Corrected Error Mask.
This register masks the reporting of corrected errors detected by the IIO local 
interfaces. An individual error control bit that is set masks error signaling of the 
particular local interface; software may set or clear the mask bit.
Note that bit fields in this register can become reserved depending on the port 
configuration. For example, if the PCIe* port is configured as 2X8 ports, then only the 
corresponding PCIe* X8 bit fields are valid.
15:5
RW1CS
0x0
pcie_err_msk:
PCIe* Error Mask
Mask bit for associated PCIe* logical ports:
Bit 5: Port 0
Bit 6: n/a
Bit 7: n/a
Bit 8: Port 2a
Bit 9: Port 2b
Bit 10: Port 2c
Bit 11: Port 2d
Bit 12: Port 3a
Bit 13: Port 3b
Bit 14: Port 3c
Bit 15: Port 3d
4:2
RV
-
Reserved1:
Reserved
1:1
RW1CS
0x0
irp1_err_msk:
IRP1 Coherent Interface Error Mask
0:0
RW1CS
0x0
irp0_err_msk:
IRP0 Coherent Interface Error Mask
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:2
Offset:
0x1a0
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:2
Offset:
0x1a4
Bit
Attr
Default
Description
31:27
RV
-
Reserved4:
Reserved.
26:26
RW1CS
0x0
mc_err_msk:
Memory Controller Error Mask.
Note: This bit is only available for Intel Xeon processor E7-2800/4800/8800 
v2 product family Product Family processor B0 stepping. For A0, the bit is 
Reserved.
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