Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
449
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.8.41 GNFERRST, GNNERRST
Global Non-Fatal FERR and NERR Status
14.8.42 IRPP[0:1]ERRST
IRP Protocol Error Status.
This register indicates the error detected by the Coherent Interface.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:2
Offset:
0x1dc
, 0x1e8
Bit
Attr
Default
Description
31:26
RV
-
Reserved1:
Reserved
25:0
ROS_V
0x0
log:
This field logs the global error status register content when the first fatal 
error is reported. This has the same format as the global fatal error status 
register (GFERRST).
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:2
Offset:
0x1ec
, 0x1f8
Bit
Attr
Default
Description
31:26
RV
-
Reserved1:
Reserved
25:0
ROS_V
0x0
log:
This filed logs the global error status register content when the first non-fatal 
error is reported. This has the same format as the global non-fatal error 
status register (GNERRST).
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:2
Offset:
0x230, 0x2b0
Bit
Attr
Default
Description
31:15
RV
-
Reserved4:
Reserved
14:14
RW1CS
0x0
protocol_parity_error: (DB)
Originally used for detecting parity error on coherent interface, however, no 
parity checks exist. So this logs parity errors on data from the IIO switch on 
the inbound path.
13:13
RW1CS
0x0
protocol_qt_overflow_underflow: (DA)
12:11
RV
-
Reserved3:
Reserved
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