Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
452
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.8.45 IRPP[0:1]FFERRHD[0:3]
IRP Protocol Fatal FERR Header Log.
Header log stores the IIO data path header information of the associated IRP Protocol 
error. The header indicates where the error is originating from and the address of the 
cycle. The header information will be varies according the four error types: Message, 
Memory/IO Request, Configure Request and Completion.
The IRP Protocol Fatal FERR Header totally has 128 bits. Refer to the below table for the 
mapping between Header and IRPP[0:1]FFERRHD[0:3] registers. 
For the Message Type, the IRP Protocol Fatal FERR Header information as below:
12:11
RV
-
Reserved3:
Reserved
10:10
ROS_V
0x0
protocol_rcvd_unexprsp: (D7)
A completion has been received from the Coherent Interface that was 
unexpected.
9:5
RV
-
Reserved2:
Reserved
4:4
ROS_V
0x0
csr_acc_32b_unaligned: (C3)
3:3
ROS_V
0x0
wrcache_uncecc_error: (C2)
A double bit ECC error was detected within the Write Cache.
2:2
ROS_V
0x0
protocol_rcvd_poison: (C1)
A poisoned packet has been received from the Coherent Interface.
1:1
ROS_V
0x0
wrcache_correcc_error: (B4)
A single bit ECC error was detected and corrected within the Write Cache.
0:0
RV
-
Reserved1:
Reserved
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:2
Offset:
IRP0: 0x238, 0x23c
IRP1: 0x2b8, 
 0x2bc
Bit
Attr
Default
Description
Bit
Register
Offset
127:96
IRPP[0:1]FFERRHD3
0x24c(IRPP0), 0x2cc(IRPP1)
95:64
IRPP[0:1]FFERRHD2
0x248(IRPP0), 0x2c8(IRPP1)
63:32
IRPP[0:1]FFERRHD1
0x244(IRPP0), 0x2c4(IRPP1)
31:0
IRPP[0:1]FFERRHD0
0x240(IRPP0), 0x2c0(IRPP1)
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