Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
463
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
31:31
ROS_V
0x0
TD:
TLP Digest.
A value of “1” in this field indicates the presence of a single DW TLP digest 
at the end of the packet for use in ECRC protection as defined by the 
PCIe* specification. 
Note: Intel Xeon processor E7-2800/4800/8800 v2 product family Product 
Family IIO does not support ECRC generation/checking so the switch does 
not store/forward ECRC.
30:30
ROS_V
0x0
EP:
Error Poisoned.
This field is used to indicate that the data payload contained in the packet 
is poisoned. 
29:28
ROS_V
0x0
Attr[1:0]:
Attributes.
These provide hints as to how the packet should be handled: 
Bit 1 set to “1” indicates Relaxed Ordering.
Bit 0 set to “1” indicates No Snoop.
This field must be set to all 0’s for configuration requests, I/O requests, 
message requests, and message signaled interrupts.
27:26
ROS_V
0x0
SwRID[6:5]:
Switch Routing ID.
This field is concatenated with SwRID[4:0] to form SwRID[6:0]. 
SwRID[6:0] is not part of the PCIe* specification (that is, these bit 
positions are reserved in the PCIe* spec.).This field facilitates routing of 
completions through the switch. 
The upper five bits correspond to the switch port number assigned to the 
agent that originated the request and are used by the switch to route the 
completion. The lower two bits are provided for each agent to assign 
according to its own internal algorithm if needed for facilitating routing 
within the agent. 
The value in this field must be preserved from the original request 
requiring a completion and transferred into the completion.
25:16
ROS_V
0x0
Length[9:0]:
Data Length.
The data length is specified in DW (4-byte). For I/O and configuration 
requests, this field must be set to 1. This field is reserved for packets that 
do not contain or refer to data payloads.
15:15
ROS_V
0x0
MAbort:
Master Abort Hint. 
This field is not part of the PCIe* spec. This field is used by the PCIe*/DMI 
interface block to indicate that the switch should master abort a request; 
this would happen if the PCIe* block received an unsupported request.
14:12
ROS_V
0x0
TC[2:0]:
Traffic Class.
This allows differentiation of transactions into eight traffic service classes 
within the PCIe* interconnect fabric only. For I/O and configuration 
requests, this field must be set to all 0’s.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:2
Offset:
IRPP0: 0x240, 
Size: 128 bits
IRPP1: 0x2c0 
Bit
Attr
Default
Description
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