Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
474
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.8.62 MINFERRST, MINNERRST
Miscellaneous Non-Fatal FERR and NERR Status.
14.8.63 MINFERRHDR_[0:3]
Miscellaneous Non-Fatal FERR Header Log.
43:0
ROS_V
0x0
vpp_enaddr:
Assigns the VPP address of the device on the VPP interface and assigns 
the port address for the ports within the VPP device. There are more 
address bits then root ports so assignment must be spread across VPP 
ports.
Port  Addr  
Root Port
[43]  [42:40]     Port 3d
[39]  [38:36]     Port 3c
[35]  [34:32]     Port 3b
[31]  [30:28]    Port 3a
[27]  [27:24]    Port 2d
[23]  [22:20]    Port 2c
[19]  [18:16]    Port 2b
[15]  [14:12]    Port 2a
[11]  [10:8]      Unused
[7]    [6:4]        Unused
[3]    [2:0]        Port 0 (PCIe* mode only) 
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5
Function:
2
Offset:
0x38c
Size: 128 bits
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5
Function:
2
Offset:
0x3a0, 0x3b4
Bit
Attr
Default
Description
31:11
RV
-
Reserved.
10:0
ROS_V
0x0
mi_err_st_log:
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5
Function:
2
Offset:
0x3a4, 0x3a8, 0x3ac, 0x3b0
Bit
Attr
Default
Description
31:0
ROS_V
0x0
hdr:
Logs the first DWORD of the header on an error condition.
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