Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
477
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.9.3
PCICMD
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x4
Bit
Attr
Default
Description
15:11
RV
-
Reserved. 
10:10
RO
0x0
intxdisable:
N/A for these devices.
9:9
RO
0x0
fb2be:
Not applicable to PCI Express and is hardwired to 0.
8:8
RO
0x0
serre:
This bit has no impact on error reporting from I/OxAPIC.
7:7
RO
0x0
idsel:
Not applicable to internal device. Hardwired to 0.
6:6
RO
0x0
perrrsp:
This bit has no impact on error reporting from I/OxAPIC.
5:5
RO
0x0
vga:
Not applicable to internal device. Hardwired to 0.
4:4
RO
0x0
memwrinv:
Not applicable to internal device. Hardwired to 0.
3:3
RO
0x0
spcen:
Not applicable. Hardwired to 0.
2:2
RW
0x0
bme:
When this bit is set, I/OxAPIC can generate MSI interrupts else not.
1:1
RW
0x0
mse:
When this bit is set, I/OxAPIC decodes the MBAR address region for accesses 
from OS/BIOS, else it cannot. Note ABAR range decode is not affected by 
this bit. Side note: Any accesses via message channel or JTAG mini port to 
registers pointed to by the MBAR address, are not gated by this bit being set 
that is, even if this bit is a 0, message channel accesses to the registers 
pointed to by MBAR address are allowed/completed normally. These 
accesses are accesses from internal microcode/PCU microcode and JTAG and 
they are allowed to access the registers normally even if this bit is clear.
0:0
RO
0x0
iose:
Hardwired to 0 since these devices don’t decode any IO BARs.
downloadlike
ArtboardArtboardArtboard
Report Bug