Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
480
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.9.8
HDR
14.9.9
MBAR
I/OxAPIC Based Address.
14.9.10 SVID
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0xe
Bit
Attr
Default
Description
7:7
RO
0x1
multi_function_device:
This bit defaults to 1b since all these devices are multifunction
6:0
RO
0x0
configuration_layout:
This field identifies the format of the configuration header layout. It is Type 0 
for all these devices. The default is 00h, indicating a “endpoint device”.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x10
Bit
Attr
Default
Description
31:12
RW
0x0
bar:
This marks the 4KB aligned 32-bit base address for memory-mapped 
registers of I/OxAPICSide note: Any accesses via message channel or JTAG 
mini port to registers pointed to by the MBAR address, are not gated by MSE 
bit (in PCICMD register) being set that is, even if MSE bit is a 0, message 
channel accesses to the registers pointed to by MBAR address are 
allowed/completed normally. These accesses are accesses from internal 
micro-code/PCU microcode and JTAG and they are allowed to access the 
registers normally even if this bit is clear.
11:4
RV
-
Reserved.
3:3
RO
0x0
prefetchable:
The I/OxAPIC registers are not prefetchable.
2:1
RO
0x0
type:
The IOAPIC registers can only be placed below 4G system address space.
0:0
RO
0x0
memory_space:
This Base Address Register indicates memory space.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x2c
Bit
Attr
Default
Description
15:0
RW_O
0x8086
svid_reg:
The default value specifies Intel but can be set to any value once after reset.
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