Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
482
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.9.15 ABAR
I/OxAPIC Alternate BAR.
14.9.16 PXPCAP
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x40
Bit
Attr
Default
Description
15:15
RW
0x0
abar_enable:
When set, the range FECX_YZ00 to FECX_YZFF is enabled as an alternate 
access method to the I/OxAPIC registers and these addresses are claimed by 
the IIO’s internal I/OxAPIC regardless of the setting the MSE bit in the 
I/OxAPIC config space. Bits “XYZ” are defined below.Side note: Any accesses 
via message channel or JTAG mini port to registers pointed to by the ABAR 
address, are not gated by this bit being set that is, even if this bit is a 0, 
message channel accesses to the registers pointed to by ABAR address are 
allowed/completed normally. These accesses are accesses from internal 
micro-code/PCU microcode and JTAG and they are allowed to access the 
registers normally even if this bit is clear.
14:12
RV
-
Reserved.
11:8
RW
0x0
base_address_19:
16 (XBAD) These bits determine the high order bits of the I/O APIC address 
map. When a memory address is recognized by the IIO which matches 
FECX_YZ00-to-FECX_YZFF, the IIO will respond to the cycle and access the 
internal I/O APIC.
7:4
RW
0x0
base_address_15:
12 (YBAD) These bits determine the low order bits of the I/O APIC address 
map. When a memory address is recognized by the IIO which matches 
FECX_YZ00-to-FECX_YZFF, the IIO will respond to the cycle and access the 
internal I/O APIC.
3:0
RW
0x0
base_address_11:
8 (ZBAD) These bits determine the low order bits of the I/O APIC address 
map. When a memory address is recognized by the IIO which matches 
FECX_YZ00-to-FECX_YZFF, the IIO will respond to the cycle and access the 
internal I/O APIC.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x44
Bit
Attr
Default
Description
31:30
RV
-
Reserved.
29:25
RO
0x0
interrupt_message_numnber:
1
24:24
RO
0x0
slot_implemented:
23:20
RO
0x9
device_port_type:
Device type is Root Complex Integrated Endpoint
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