Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
489
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.9.27 IOREMGPECNT
Remote I/O GPE Count.
14.9.28 FAUXGV
14.10
Device 5 Function 4 I/OxAPIC
I/OxAPIC has a direct memory mapped space. An index/data register pair is located 
within the directed memory mapped region and is used to access the redirection table 
entries. The offsets shown in the table are from the base address in either ABAR or 
MBAR or both.
Note:
Access to addresses beyond 0x40h return all 0s.
Only addresses up to offset 0xFF can be accessed via the ABAR register whereas offsets 
up to 0xFFF can be accessed via MBAR. 
Only aligned DWORD reads and write are allowed towards the I/OxAPIC memory space. 
Any other accesses will result in an error.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x2ac
Bit
Attr
Default
Description
31:24
RV
-
Reserved.
23:16
RW_V
0x0
hpgpe_cnt:
Number of remote HPGPEs received.
15:8
RW_V
0x0
pmgpe_cnt:
Number of remote PMGPEs received.
7:0
RW_V
0x0
gpe_cnt:
Number of remote GPEs received.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x2c4
Bit
Attr
Default
Description
31:1
RV
-
Reserved.
0:0
RWS_L
0x0
FauxGVEn:
Enable Fault GV.
Register name
Offset
Size
INDEX
0x0
8
WINDOW
0x10
32
EOI
0x40
8
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