Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
493
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.10.4.3 ARBID__WINDOW
This is a legacy register carried over from days of serial bus interrupt delivery. This 
register has no meaning in IIO. It just tracks the APICID register for compatibility 
reasons. 
14.10.4.4 BCFG__WINDOW
14.10.4.5 RTL[0:23]__WINDOW
The information in this register along with Redirection Table High DWORD register is 
used to construct the MSI interrupt. There is one of these pairs of registers for every 
interrupt. The first interrupt has the redirection registers at offset 10h. The second 
interrupt at 12h, third at 14h, and so forth, until the final interrupt (interrupt 23) at 
3Eh.
Type:
MEM
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x2
Bit
Attr
Default
Description
31:28
RV
-
Reserved.
27:24
RO
0x0
arbitration_id:
Just tracks the APICID register.
23:0
RV
-
Reserved.
Type:
MEM
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x3
Bit
Attr
Default
Description
31:1
RV
-
Reserved.
0:0
RW
0x1
boot_configuration:
This bit is a default1 to indicate FSB delivery mode. A value of 0 has no effect. 
Its left as RW for software compatibility reasons. 
Type:
MEM
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e, 
0x20, 0x22, 0x24, 0x26, 0x28, 0x2a,  0x2c, 0x2e,
0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e
Bit
Attr
Default
Description
31:18
RV
-
Reserved.
17:17
RW
0x0
disable_flushing:
This bit has no meaning in IIO. This bit is R/W for software compatibility 
reasons only
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