Intel E7-8891 v2 CM8063601377422 User Manual

494

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

16:16

RW

0x1

msk:

When cleared, an edge assertion or level (depending on bit 15 in this 

register) on the corresponding interrupt input results in delivery of an MSI 

interrupt using the contents of the corresponding redirection table high/low 

entry. When set, an edge or level on the corresponding interrupt input does 

not cause MSI Interrupts and no MSI interrupts are held pending as well 

(that is, if an edge interrupt asserted when the mask bit is set, no MSI 

interrupt is sent and the hardware does not remember the event to cause an 

MSI later when the mask is cleared). When set, assertion/deassertion of the 

corresponding interrupt input causes Assert/Deassert_INTx messages to be 

sent to the legacy ICH, provided the ‘Disable PCI INTx Routing to ICH’ bit is 

clear. If the latter is set, Assert/Deassert_INTx messages are not sent to the 

legacy ICH.
When mask bit goes from 1 to 0 for an entry and the entry is programmed 

for level input, the input is sampled and if asserted, an MSI is sent. Also, if 

an Assert_INTx message was previously sent to the legacy ICH/internal-

coalescing logic on behalf of the entry, when the mask bit is clear, then a 

Deassert_INTx event is scheduled on behalf of the entry (whether this event 

results in a Deassert_INTx message to the legacy ICH depends on whether 

there were other outstanding Deassert_INTx messages from other sources). 

When the mask bit goes from 0 to 1, and the corresponding interrupt input is 

already asserted, an Assert_INTx event is scheduled on behalf of the entry. 

Note though that if the interrupt is deasserted when the bit transitions from 

0 to 1, a Deassert_INTx is not scheduled on behalf of the entry. 

15:15

RW

0x0

tm:

This field indicates the type of signal on the interrupt input that triggers an 

interrupt. 0 indicates edge sensitive, 1 indicates level sensitive. 

14:14

RO

0x0

rirr:

This bit is used for level triggered interrupts; its meaning is undefined for 

edge triggered interrupts. For level triggered interrupts, this bit is set when 

an MSI interrupt has been issued by the I/OxAPIC into the system fabric 

(noting that if BME bit is clear or when the mask bit is set, no new MSI 

interrupts cannot be generated and this bit cannot transition from 0 to 1 in 

those conditions). It is reset (if set) when an EOI message is received from a 

local APIC with the appropriate vector number, at which time the level 

interrupt input corresponding to the entry is resampled causing one more 

MSI interrupt (if other enable bits are set) and causing this bit to be set 

again. 

13:13

RW

0x0

ip:

0=active high; 1=active low. Strictly, speaking this bit has no meaning in IIO 

since the Assert/Deassert_INTx messages are level in-sensitive. But the core 

I/OxAPIC logic that is reused from PXH might be built to use this bit to 

determine the correct polarity. Most OS’es today support only active low 

interrupt inputs for PCI devices. Given that, the OS is expected to program a 

1 into this register and so the ’internal’ virtual wire signals in the IIO need to 

be active low that is, 0=asserted and 1=deasserted.

12:12

RO

0x0

delivery_status:

When trigger mode is set to level and the entry is unmasked, this bit 

indicates the state of the level interrupt that is, 1b if interrupt is asserted 

else 0b. When the trigger mode is set to level but the entry is masked, this 

bit is always 0b. This bit is always 0b when trigger mode is set to edge. 

11:11

RW

0x0

dstm:

0 - Physical1 - Logical