Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
499
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.11.5 RID
14.11.6 CCR
Accesses to the CCR field are redirected to the UBox due to DWORD alignment.
14.11.7 CLSR
Type:
CFG
PortID:
N/A
Bus:
0
Device:
6Function:0,3
Bus:
0
Device:
7Function:0
Offset:
0x8
Bit
Attr
Default
Description
7:0
RO_V
0x0
revision_id:
Reflects the Uncore Revision ID after reset.
Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID 
register in any Intel Xeon processor E7-2800/4800/8800 v2 product family 
Product Family function.
Implementation Note:
Read and write requests from the host to any RID register in any Intel Xeon 
processor E7-2800/4800/8800 v2 product family Product Family function are 
redirected to the UBox.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
6Function:0,3
Bus:
0
Device:
7Function:0
Offset:
0x9
Bit
Attr
Default
Description
23:16
RO
0x08
base_class:
Generic Device
15:8
RO
0x80
sub_class:
Generic Device
7:0
RO
0x0
interface:
Set to 00h for all non-APIC devices.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
6Function:0,3
Bus:
0
Device:
7Function:0
Offset:
0xc
Bit
Attr
Default
Description
7:0
RW
0x0
cacheline_size:
This register is set as RW for compatibility reasons only. Cacheline size is 
always 64B.
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