Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
502
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.11.16 MINGNT
14.11.17 MAXLAT
14.11.18 PXPCAP
Type:
CFG
PortID:
N/A
Bus:
0
Device:
6Function:0,3
Bus:
0
Device:
7Function:0
Offset:
0x3e
Bit
Attr
Default
Description
7:0
RO
0x0
mgv:
Not applicable and hardwired to 0.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
6Function:0,3
Bus:
0
Device:
7Function:0
Offset:
0x3f
Bit
Attr
Default
Description
7:0
RO
0x0
mlv:
Not applicable and hardwired to 0.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
6Function:0,3
Bus:
0
Device:
7Function:0
Offset:
0x40
Bit
Attr
Default
Description
31:30
RV
-
Reserved.
29:25
RO
0x0
interrupt_message_number:
N/A for this device
24:24
RO
0x0
slot_implemented:
N/A for integrated endpoints
23:20
RO
0x9
device_port_type:
Device type is Root Complex Integrated Endpoint
19:16
RO
0x1
capability_version:
PCI Express Capability is Compliant with Version 1.0 of the PCI Express 
Spec.
Note:
This capability structure is not compliant with Versions beyond 1.0, since 
they require additional capability registers to be reserved. The only purpose 
for this capability structure is to make enhanced configuration space 
available. Minimizing the size of this structure is accomplished by reporting 
version 1.0 compliancy and reporting that this is an integrated root port 
device. As such, only three Dwords of configuration space are required for 
this structure.
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