Intel E7-8891 v2 CM8063601377422 User Manual
Product codes
CM8063601377422
Reliability, Availability, Serviceability, and Manageability
56
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
7.4.4.2
Rank Sparing
7.4.4.2.1
Usage
Rank sparing enables a failing rank to be replaced by ranks installed in an
unused space. An unused spare rank on the channel can be used to copy the contents
of a failing rank on that channel.
unused space. An unused spare rank on the channel can be used to copy the contents
of a failing rank on that channel.
Note:
The iMC will not support sparing across sockets or SMI2 channels.
7.4.5
Single Device Data Correction (SDDC)
Single Device Data Correction refers to the ability of the error correction code to correct
errors resulting from the failure of a single DRAM device. In independent channel
mode, Intel Xeon processor E7 v2 product family’s ECC hardware can correct errors in a
single x4 DRAM device. In lockstep mode, Intel Xeon processor E7 v2 product family’s
ECC hardware can correct errors in a single x8 DRAM device.
errors resulting from the failure of a single DRAM device. In independent channel
mode, Intel Xeon processor E7 v2 product family’s ECC hardware can correct errors in a
single x4 DRAM device. In lockstep mode, Intel Xeon processor E7 v2 product family’s
ECC hardware can correct errors in a single x8 DRAM device.
7.4.6
Double Device Data Correction (DDDC)
Double Device Data Correction refers to the ability of the error correction code to
correct errors resulting from the failure of two DRAM devices. In lockstep mode, Intel
Xeon processor E7 v2 product family’s ECC hardware can correct errors in two x4 DRAM
devices provided the failures are separated in time.
correct errors resulting from the failure of two DRAM devices. In lockstep mode, Intel
Xeon processor E7 v2 product family’s ECC hardware can correct errors in two x4 DRAM
devices provided the failures are separated in time.
7.4.7
+1 Bit Correction Beyond Device Correction
Intel Xeon processor E7 v2 product family’s ECC hardware will support correcting single
bit errors beyond the device failure corrected by SDDC/DDDC after the device has been
tagged.
bit errors beyond the device failure corrected by SDDC/DDDC after the device has been
tagged.
7.4.8
PECI Write Accessibility to iMC Registers
PECI has full read access to CSRs in iMC, but write access is limited to a select few
registers.
registers.
7.4.9
iMC Error Handling
Memory Controller errors are handled according to the IA-32 Machine
Check Architecture.
Check Architecture.
7.4.9.1
Error Severity
Intel Xeon processor E7 v2 product family supports 3 of the 4 possible combinations of
“Uncorrectable Error” and “Processor State Corrupted” bits in the IA-32 Machine Check
Bank. Thus, all Memory Controller errors are categorized as either Corrected,
Uncorrected Non-Fatal, or Fatal.
“Uncorrectable Error” and “Processor State Corrupted” bits in the IA-32 Machine Check
Bank. Thus, all Memory Controller errors are categorized as either Corrected,
Uncorrected Non-Fatal, or Fatal.
7.4.10
Intel SMI2 Half-Width Failover Mode
When persistent SouthBound errors are detected on either the Intel SMI2 data bus or
the Intel SMI2 CMD# bus, rather than shutting down the entire system, the memory
controller will transition to Half-Width Failover mode.
the Intel SMI2 CMD# bus, rather than shutting down the entire system, the memory
controller will transition to Half-Width Failover mode.