Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
59
Datasheet Volume Two: Functional Description, February 2014
Reliability, Availability, Serviceability, and Manageability
7.5.3.3.1
PCIe Error Severity Mapping
PCIe errors can be classified as two types: Uncorrectable errors and Correctable errors. 
Uncorrectable errors can further be classified as Fatal or Non-Fatal. This classification is 
compatible and mapped with IO module’s error classification: Correctable as 
Correctable, Non-Fatal as Recoverable, and Fatal as Fatal.
7.5.3.3.2
Unsupported Transactions and Unexpected Completions
If the IO module receives a legal PCIe defined packet that is not included in PCIe 
supported transactions, then the IO module treats that packet as an unsupported 
transaction and follows the PCIe rules for handling unsupported requests. If the IO 
module receives a completion with a requester ID set to the root port requester ID and 
there is no matching request outstanding, then this is considered an “Unexpected 
Completion”. Also, the IO module detects malformed packets from Express and reports 
them as errors per the Express specification rules.
7.5.3.3.3
Error Forwarding
PCIe has a concept called Error Forwarding or Data Poisoning. This feature allows a 
PCIe device to forward data errors across the interface without it being interpreted as 
an error originating on that interface. The IO module forwards the poison bit from the 
coherency interface to PCIe and vice-versa and also between PCI Express ports on peer 
to peer.
7.5.3.3.4
Unconnected Ports
If a transaction targets a PCIe link that is not connected to any device or the link is 
down (DL_Down status), the IO module treats that as a master abort situation. 
7.6
System Level RAS Features
The Intel Xeon processor E7 v2 product family processor incorporates several features 
and interfaces to support system manageability, system debugging, system 
configuration, performance, and other miscellaneous functions. SMBus, PECI and JTAG 
Test Access Port provide the protocol interfaces for access to configuration registers. 
The Intel Xeon processor E7 v2 product family provides PECI (Platform Environment 
Control Interface) for external management devices such as BMC to monitor and 
manage fan speed and power/thermal states, and to read out the MCA global and MC 
bank MSRs. The Intel Xeon processor E7 v2 product family processor supports the PECI 
revision 3.0.
The Intel Xeon processor E7 v2 product family processor also implements three SMbus 
masters. 
Following sections describe a few key system level RASM features:
• Time-out  Timer  Schemes
• Processor BIST
• Fault Resilient Boot - Socket disable and core disable
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