Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
61
Datasheet Volume Two: Functional Description, February 2014
Reset Flow
8
Reset Flow
This chapter describes the reset flow for the Intel Xeon processor E7 v2 product family 
as applicable to the platform.
8.1
Introduction
The processor supports the following reset types: Cold Reset (also known as PowerOn 
Reset) and Warm Reset. 
The Cold Reset provides the baseline framework for the Warm Reset flow: in general, 
the flows are identical, except in cases where a particular step required for Cold Reset 
may be skipped.
8.1.1
Cold Reset
Cold reset is the power on reset, and is the first time when the platform asserts 
PWRGOOD and asserts RESET_N to the CPU. The platform has to wait for the Base 
Clock (BCLK) and the power to be stable before asserting PWRGOOD. 
This results in reset of all the states in the processor, including the sticky state that is 
preserved on a warm reset. All the PLLs are calibrated and clocked, I/O (DMI2, Intel
®
 
QPI, PCI Express, and DDR3) links undergo initialization and calibration according to 
the strap setting. Components in fixed and variable power planes are brought up. Ring, 
router, SAD, and various lookup tables in the core/cbo are initialized. Once the uncore 
initialization has completed, then the power is enabled to the cores and cores are 
brought out of reset. BIOS is fetched either from PCH (if the socket is strapped as such) 
or fetched over the Intel
®
 QPI links.
8.1.2
Warm Reset
Warm reset is typically a platform-wide event and is indicated to the processor socket 
by assertion and de-assertion of the RESET_N signal pin; CPU Hot-Add/-Onlining is an 
obvious exception. The warm reset preserves the error log state and machine check 
bank states for use by platform for post error event analysis and debug.
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