Intel E7-8891 v2 CM8063601377422 User Manual

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Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
Ubox Functional Description
Ubox Functional Description
Ubox Overview
The UBOX is the piece of logic that deals with the non mainstream flows in the system. 
This includes transactions like the register accesses, interrupt flows, lock flows and 
events. The UBOX also serves as the coordination point for the PCU for power 
management flows. In addition, the UBOX houses co-ordination for the perfmon 
architecture, and also houses scratch pad registers and semaphore registers.
The Intel Xeon processor E7 v2 product family Ubox supports the 
following functionalities:
• Interrupt delivery. The UBOX broadcast interrupt indications to all cores in the 
package and also across sockets. In the process, it also takes into account interrupt 
redirection and filtering in order to ensure overall power savings.
• UBOX handshakes with PCU to wake-up cores when interrupt request arrives. The 
UBOX also co-ordinates various power management flows from the PCU.
• The UBOX also serves as the Intel QPI lock and quiesce master in the system. 
• UBOX decodes and routes transactions to uncore control registers. 
• The UBOX also serves as the point for event handling and delivery in the uncore.
• The UBOX also implements miscellaneous functionality in the uncore, such as time 
stamp counters, scratch pads, semaphores, perfmon infrastructure support, etc.
Interrupt and Event Delivery
There are several types of events that are handled by the UBOX:
• IPI - interrupt messages sent by one core to other cores
• MSI - interrupt messages sent by devices (including IOAPIC)
• VLW - special messages that replace wires uses in previous generations
• Internal Events - events generated in various uncore functions (except PCU) and 
are sent to the core.
Scratchpad Registers
In addition to registers, which are part of UBOX functionality, UBOX provides 
scratchpad registers for BIOS to use. 
Sideband Interfaces
There are various kinds of sideband interfaces that are supported in Intel Xeon 
processor E7 v2 product family. These include PECI and TAP.
PECI Access
PECI is a sideband interface that allows the manageability engine, or a BMC (baseboard 
management controller) to access the uncore registers using a sideband interface. 
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