Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
77
Datasheet Volume Two: Functional Description, February 2014
Registers Overview and Configuration Process
12.2.1.4
Unimplemented Devices/Functions and Registers
Configuration reads to unimplemented functions and devices will return all ones 
emulating a master abort response. Note that there is no asynchronous error reporting 
that happens when a configuration read master aborts. Configuration writes to 
unimplemented functions and devices will return a normal response. 
Software should not attempt or rely on reads or writes to unimplemented registers or 
register bits. Unimplemented registers should return all zeroes when read. Writes to 
unimplemented registers are ignored. For configuration writes to these register (require 
a completion), the completion is returned with a normal completion status (not master-
aborted).
12.2.1.5
Device Hiding
The Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family provides a 
mechanism by which various PCI devices or functions within the unit can be hidden 
from the host configuration software i.e. all PCI configuration accesses to the devices’ 
configuration space from Intel
®
QPI will be master aborted. This mechanism is needed 
in cases where a device or function is not used or is available for use, because either 
the device is turned off or the device is not serving any meaningful purpose in a given 
platform configuration. 
This hiding mechanism is implemented via the DEVHIDE register:
Integrated Memory Controller 1
EB0h, 
EB1h,
EB4h,
EB5h
30
0, 
1, 
4, 
5
Channel 2 Thermal Control,
Channel 3 Thermal Control, 
Channel 0 Thermal Control,
Channel 1 Thermal Control
Integrated Memory Controller 
EF8h,
EF9h,
EFAh,
EFBh,
EFCh,
EFDh
17
0,
1,
2,
3,
4,
5
SMI2 (VMSE) 1 Normal
SMI2 (VMSE) 1 EXT
SMI2 (VMSE) MCAST 0+1 Normal
SMI2 (VMSE) MCAST 0+1 EXT
SMI2 (VMSE) 0 Normal
SMI2 (VMSE) 0 EXT
Integrated Memory Controller 
ED8h,
ED8h,
EDCh,
EDDh,
EDEh,
EDFh
31
0,
1,
4,
5,
6,
7
SMI2 (VMSE) 3 Normal
SMI2 (VMSE) 3 EXT
SMI2 (VMSE) 2 Normal
SMI2 (VMSE) 2 EXT
SMI2 (VMSE) MCAST 2+3 Normal
SMI2 (VMSE) MCAST 2+3 EXT
R2PCIe
E1Dh
19
0
Processor Ring to PCIE
R2PCIe
E74h,
E75h
20
2,
3
R2PCIE 
R2PCIe
E34h
19
1
Processor Ring to PCIE Performance 
Monitoring
R3 Intel
®
QPI Link 0 & 1 
Performance
E36h,
E37h
19
5,
6
Intel
®
QPI 0 & 1 Ring Performance 
Monitoring
R3 Intel
®
QPI Link 2 Performance
E3Eh,
E3Fh
18
5,
6
Intel
®
QPI 2 Ring Performance 
Monitoring
R3 Intel
®
QPI 0 & 1
E81h
19
4
Intel
®
QPI 0 & 1 Ring Registers
R3 Intel
®
QPI 2
E41h
18
4
Intel
®
QPI 2 Ring Registers
Table 12-1. Functions specifically handled by the processor (Sheet 3 of 3)
Register Group
DID
Device
Function
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